VER_NO: 369d2d860d34e777c0f7d545a7dfc3c4
EFUSES:
  WR_DIS               : {show: y, blk : 0, word: 0, pos : 0, len : 16, start  : 0, type : 'uint:16', wr_dis   : 1, rd_dis: null, alt                            : '', dict             : '', desc: Efuse write disable mask, rloc: 'EFUSE_BLK0_RDATA0_REG[15:0]', bloc: 'B0,B1'}
  RD_DIS               : {show: y, blk : 0, word: 0, pos: 16, len  : 4, start : 16, type  : 'uint:4', wr_dis   : 0, rd_dis: null, alt                            : '', dict             : '', desc: Disable reading from BlOCK1-3, rloc: 'EFUSE_BLK0_RDATA0_REG[19:16]', bloc: 'B2[3:0]'}
  FLASH_CRYPT_CNT      : {show: y, blk : 0, word: 0, pos: 20, len  : 7, start : 20, type  : 'uint:7', wr_dis   : 2, rd_dis: null, alt                            : '', dict             : '', desc: Flash encryption is enabled if this field has an odd number of bits set, rloc: 'EFUSE_BLK0_RDATA0_REG[26:20]', bloc: 'B2[7:4],B3[2:0]'}
  UART_DOWNLOAD_DIS    : {show: y, blk : 0, word: 0, pos: 27, len  : 1, start : 27, type      : bool, wr_dis   : 2, rd_dis: null, alt                            : '', dict             : '', desc: Disable UART download mode. Valid for ESP32 V3 and newer; only, rloc: 'EFUSE_BLK0_RDATA0_REG[27]', bloc: 'B3[3]'}
  RESERVED_0_28        : {show: n, blk : 0, word: 0, pos: 28, len  : 4, start : 28, type  : 'uint:4', wr_dis: null, rd_dis: null, alt                            : '', dict             : '', desc: reserved, rloc: 'EFUSE_BLK0_RDATA0_REG[31:28]', bloc: 'B3[7:4]'}
  MAC                  : {show: y, blk : 0, word: 1, pos : 0, len : 48, start : 32, type : 'bytes:6', wr_dis   : 3, rd_dis: null, alt                   : MAC_FACTORY, dict             : '', desc: MAC address, rloc: EFUSE_BLK0_RDATA1_REG, bloc: 'B4,B5,B6,B7,B8,B9'}
  MAC_CRC              : {show: y, blk : 0, word: 2, pos: 16, len  : 8, start : 80, type  : 'uint:8', wr_dis   : 3, rd_dis: null, alt               : MAC_FACTORY_CRC, dict             : '', desc: CRC8 for MAC address, rloc: 'EFUSE_BLK0_RDATA2_REG[23:16]', bloc: B10}
  RESERVE_0_88         : {show: n, blk : 0, word: 2, pos: 24, len  : 8, start : 88, type  : 'uint:8', wr_dis: null, rd_dis: null, alt                            : '', dict             : '', desc: Reserved; it was created by set_missed_fields_in_regs func, rloc: 'EFUSE_BLK0_RDATA2_REG[31:24]', bloc: B11}
  DISABLE_APP_CPU      : {show: y, blk : 0, word: 3, pos : 0, len  : 1, start : 96, type      : bool, wr_dis   : 3, rd_dis: null, alt          : CHIP_VER_DIS_APP_CPU, dict             : '', desc: Disables APP CPU, rloc: 'EFUSE_BLK0_RDATA3_REG[0]', bloc: 'B12[0]'}
  DISABLE_BT           : {show: y, blk : 0, word: 3, pos : 1, len  : 1, start : 97, type      : bool, wr_dis   : 3, rd_dis: null, alt               : CHIP_VER_DIS_BT, dict             : '', desc: Disables Bluetooth, rloc: 'EFUSE_BLK0_RDATA3_REG[1]', bloc: 'B12[1]'}
  CHIP_PACKAGE_4BIT    : {show: y, blk : 0, word: 3, pos : 2, len  : 1, start : 98, type      : bool, wr_dis: null, rd_dis: null, alt             : CHIP_VER_PKG_4BIT, dict             : '', desc: 'Chip package identifier #4bit', rloc: 'EFUSE_BLK0_RDATA3_REG[2]', bloc: 'B12[2]'}
  DIS_CACHE            : {show: y, blk : 0, word: 3, pos : 3, len  : 1, start : 99, type      : bool, wr_dis   : 3, rd_dis: null, alt            : CHIP_VER_DIS_CACHE, dict             : '', desc: Disables cache, rloc: 'EFUSE_BLK0_RDATA3_REG[3]', bloc: 'B12[3]'}
  SPI_PAD_CONFIG_HD    : {show: y, blk : 0, word: 3, pos : 4, len  : 5, start: 100, type  : 'uint:5', wr_dis: null, rd_dis: null, alt                            : '', dict             : '', desc: read for SPI_pad_config_hd, rloc: 'EFUSE_BLK0_RDATA3_REG[8:4]', bloc: 'B12[7:4],B13[0]'}
  CHIP_PACKAGE         : {show: y, blk : 0, word: 3, pos : 9, len  : 3, start: 105, type  : 'uint:3', wr_dis: null, rd_dis: null, alt                  : CHIP_VER_PKG, dict             : '', desc: Chip package identifier, rloc: 'EFUSE_BLK0_RDATA3_REG[11:9]', bloc: 'B13[3:1]'}
  CHIP_CPU_FREQ_LOW    : {show: y, blk : 0, word: 3, pos: 12, len  : 1, start: 108, type      : bool, wr_dis: null, rd_dis: null, alt                            : '', dict             : '', desc: If set alongside EFUSE_RD_CHIP_CPU_FREQ_RATED; the ESP32's max CPU frequency is rated for 160MHz. 240MHz otherwise, rloc: 'EFUSE_BLK0_RDATA3_REG[12]', bloc: 'B13[4]'}
  CHIP_CPU_FREQ_RATED  : {show: y, blk : 0, word: 3, pos: 13, len  : 1, start: 109, type      : bool, wr_dis: null, rd_dis: null, alt                            : '', dict             : '', desc: If set; the ESP32's maximum CPU frequency has been rated, rloc: 'EFUSE_BLK0_RDATA3_REG[13]', bloc: 'B13[5]'}
  BLK3_PART_RESERVE    : {show: y, blk : 0, word: 3, pos: 14, len  : 1, start: 110, type      : bool, wr_dis  : 10, rd_dis   : 3, alt                            : '', dict             : '', desc: BLOCK3 partially served for ADC calibration data, rloc: 'EFUSE_BLK0_RDATA3_REG[14]', bloc: 'B13[6]'}
  CHIP_VER_REV1        : {show: y, blk : 0, word: 3, pos: 15, len  : 1, start: 111, type      : bool, wr_dis: null, rd_dis: null, alt                            : '', dict             : '', desc: bit is set to 1 for rev1 silicon, rloc: 'EFUSE_BLK0_RDATA3_REG[15]', bloc: 'B13[7]'}
  RESERVE_0_112        : {show: n, blk : 0, word: 3, pos: 16, len : 16, start: 112, type : 'uint:16', wr_dis: null, rd_dis: null, alt                            : '', dict             : '', desc: Reserved; it was created by set_missed_fields_in_regs func, rloc: 'EFUSE_BLK0_RDATA3_REG[31:16]', bloc: 'B14,B15'}
  CLK8M_FREQ           : {show: y, blk : 0, word: 4, pos : 0, len  : 8, start: 128, type  : 'uint:8', wr_dis   : 4, rd_dis: null, alt                     : CK8M_FREQ, dict             : '', desc: 8MHz clock freq override, rloc: 'EFUSE_BLK0_RDATA4_REG[7:0]', bloc: B16}
  ADC_VREF             : {show: y, blk : 0, word: 4, pos : 8, len  : 5, start: 136, type  : 'uint:5', wr_dis   : 4, rd_dis: null, alt                            : '', dict             : '', desc: True ADC reference voltage, rloc: 'EFUSE_BLK0_RDATA4_REG[12:8]', bloc: 'B17[4:0]'}
  RESERVE_0_141        : {show: n, blk : 0, word: 4, pos: 13, len  : 1, start: 141, type      : bool, wr_dis: null, rd_dis: null, alt                            : '', dict             : '', desc: Reserved; it was created by set_missed_fields_in_regs func, rloc: 'EFUSE_BLK0_RDATA4_REG[13]', bloc: 'B17[5]'}
  XPD_SDIO_REG         : {show: y, blk : 0, word: 4, pos: 14, len  : 1, start: 142, type      : bool, wr_dis   : 5, rd_dis: null, alt                            : '', dict             : '', desc: read for XPD_SDIO_REG, rloc: 'EFUSE_BLK0_RDATA4_REG[14]', bloc: 'B17[6]'}
  XPD_SDIO_TIEH        : {show: y, blk : 0, word: 4, pos: 15, len  : 1, start: 143, type      : bool, wr_dis   : 5, rd_dis: null, alt                     : SDIO_TIEH, dict: '{1: "3.3V", 0: "1.8V"}', desc: If XPD_SDIO_FORCE & XPD_SDIO_REG, rloc: 'EFUSE_BLK0_RDATA4_REG[15]', bloc: 'B17[7]'}
  XPD_SDIO_FORCE       : {show: y, blk : 0, word: 4, pos: 16, len  : 1, start: 144, type      : bool, wr_dis   : 5, rd_dis: null, alt                    : SDIO_FORCE, dict             : '', desc: Ignore MTDI pin (GPIO12) for VDD_SDIO on reset, rloc: 'EFUSE_BLK0_RDATA4_REG[16]', bloc: 'B18[0]'}
  RESERVE_0_145        : {show: n, blk : 0, word: 4, pos: 17, len : 15, start: 145, type : 'uint:15', wr_dis: null, rd_dis: null, alt                            : '', dict             : '', desc: Reserved; it was created by set_missed_fields_in_regs func, rloc: 'EFUSE_BLK0_RDATA4_REG[31:17]', bloc: 'B18[7:1],B19'}
  SPI_PAD_CONFIG_CLK   : {show: y, blk : 0, word: 5, pos : 0, len  : 5, start: 160, type  : 'uint:5', wr_dis   : 6, rd_dis: null, alt                            : '', dict             : '', desc: Override SD_CLK pad (GPIO6/SPICLK), rloc: 'EFUSE_BLK0_RDATA5_REG[4:0]', bloc: 'B20[4:0]'}
  SPI_PAD_CONFIG_Q     : {show: y, blk : 0, word: 5, pos : 5, len  : 5, start: 165, type  : 'uint:5', wr_dis   : 6, rd_dis: null, alt                            : '', dict             : '', desc: Override SD_DATA_0 pad (GPIO7/SPIQ), rloc: 'EFUSE_BLK0_RDATA5_REG[9:5]', bloc: 'B20[7:5],B21[1:0]'}
  SPI_PAD_CONFIG_D     : {show: y, blk : 0, word: 5, pos: 10, len  : 5, start: 170, type  : 'uint:5', wr_dis   : 6, rd_dis: null, alt                            : '', dict             : '', desc: Override SD_DATA_1 pad (GPIO8/SPID), rloc: 'EFUSE_BLK0_RDATA5_REG[14:10]', bloc: 'B21[6:2]'}
  SPI_PAD_CONFIG_CS0   : {show: y, blk : 0, word: 5, pos: 15, len  : 5, start: 175, type  : 'uint:5', wr_dis   : 6, rd_dis: null, alt                            : '', dict             : '', desc: Override SD_CMD pad (GPIO11/SPICS0), rloc: 'EFUSE_BLK0_RDATA5_REG[19:15]', bloc: 'B21[7],B22[3:0]'}
  CHIP_VER_REV2        : {show: y, blk : 0, word: 5, pos: 20, len  : 1, start: 180, type      : bool, wr_dis: null, rd_dis: null, alt                            : '', dict             : '', desc: '', rloc: 'EFUSE_BLK0_RDATA5_REG[20]', bloc: 'B22[4]'}
  RESERVE_0_181        : {show: n, blk : 0, word: 5, pos: 21, len  : 1, start: 181, type      : bool, wr_dis: null, rd_dis: null, alt                            : '', dict             : '', desc: Reserved; it was created by set_missed_fields_in_regs func, rloc: 'EFUSE_BLK0_RDATA5_REG[21]', bloc: 'B22[5]'}
  VOL_LEVEL_HP_INV     : {show: y, blk : 0, word: 5, pos: 22, len  : 2, start: 182, type  : 'uint:2', wr_dis   : 3, rd_dis: null, alt                            : '', dict             : '', desc: 'This field stores the voltage level for CPU to run at 240 MHz; or for flash/PSRAM to run at 80 MHz.0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (RO)', rloc: 'EFUSE_BLK0_RDATA5_REG[23:22]', bloc: 'B22[7:6]'}
  WAFER_VERSION_MINOR  : {show: y, blk : 0, word: 5, pos: 24, len  : 2, start: 184, type  : 'uint:2', wr_dis: null, rd_dis: null, alt                            : '', dict             : '', desc: '', rloc: 'EFUSE_BLK0_RDATA5_REG[25:24]', bloc: 'B23[1:0]'}
  RESERVE_0_186        : {show: n, blk : 0, word: 5, pos: 26, len  : 2, start: 186, type  : 'uint:2', wr_dis: null, rd_dis: null, alt                            : '', dict             : '', desc: Reserved; it was created by set_missed_fields_in_regs func, rloc: 'EFUSE_BLK0_RDATA5_REG[27:26]', bloc: 'B23[3:2]'}
  FLASH_CRYPT_CONFIG   : {show: y, blk : 0, word: 5, pos: 28, len  : 4, start: 188, type  : 'uint:4', wr_dis  : 10, rd_dis   : 3, alt                : ENCRYPT_CONFIG, dict             : '', desc: Flash encryption config (key tweak bits), rloc: 'EFUSE_BLK0_RDATA5_REG[31:28]', bloc: 'B23[7:4]'}
  CODING_SCHEME        : {show: y, blk : 0, word: 6, pos : 0, len  : 2, start: 192, type  : 'uint:2', wr_dis  : 10, rd_dis   : 3, alt                            : '', dict: '{0: "NONE (BLK1-3 len=256 bits)", 1: "3/4 (BLK1-3 len=192 bits)", 2: "REPEAT (BLK1-3 len=128 bits) not supported", 3: "NONE (BLK1-3 len=256 bits)"}', desc: Efuse variable block length scheme, rloc: 'EFUSE_BLK0_RDATA6_REG[1:0]', bloc: 'B24[1:0]'}
  CONSOLE_DEBUG_DISABLE: {show: y, blk : 0, word: 6, pos : 2, len  : 1, start: 194, type      : bool, wr_dis  : 15, rd_dis: null, alt                            : '', dict             : '', desc: Disable ROM BASIC interpreter fallback, rloc: 'EFUSE_BLK0_RDATA6_REG[2]', bloc: 'B24[2]'}
  DISABLE_SDIO_HOST    : {show: y, blk : 0, word: 6, pos : 3, len  : 1, start: 195, type      : bool, wr_dis: null, rd_dis: null, alt                            : '', dict             : '', desc: '', rloc: 'EFUSE_BLK0_RDATA6_REG[3]', bloc: 'B24[3]'}
  ABS_DONE_0           : {show: y, blk : 0, word: 6, pos : 4, len  : 1, start: 196, type      : bool, wr_dis  : 12, rd_dis: null, alt                            : '', dict             : '', desc: Secure boot V1 is enabled for bootloader image, rloc: 'EFUSE_BLK0_RDATA6_REG[4]', bloc: 'B24[4]'}
  ABS_DONE_1           : {show: y, blk : 0, word: 6, pos : 5, len  : 1, start: 197, type      : bool, wr_dis  : 13, rd_dis: null, alt                            : '', dict             : '', desc: Secure boot V2 is enabled for bootloader image, rloc: 'EFUSE_BLK0_RDATA6_REG[5]', bloc: 'B24[5]'}
  JTAG_DISABLE         : {show: y, blk : 0, word: 6, pos : 6, len  : 1, start: 198, type      : bool, wr_dis  : 14, rd_dis: null, alt                  : DISABLE_JTAG, dict             : '', desc: Disable JTAG, rloc: 'EFUSE_BLK0_RDATA6_REG[6]', bloc: 'B24[6]'}
  DISABLE_DL_ENCRYPT   : {show: y, blk : 0, word: 6, pos : 7, len  : 1, start: 199, type      : bool, wr_dis  : 15, rd_dis: null, alt                            : '', dict             : '', desc: Disable flash encryption in UART bootloader, rloc: 'EFUSE_BLK0_RDATA6_REG[7]', bloc: 'B24[7]'}
  DISABLE_DL_DECRYPT   : {show: y, blk : 0, word: 6, pos : 8, len  : 1, start: 200, type      : bool, wr_dis  : 15, rd_dis: null, alt                            : '', dict             : '', desc: Disable flash decryption in UART bootloader, rloc: 'EFUSE_BLK0_RDATA6_REG[8]', bloc: 'B25[0]'}
  DISABLE_DL_CACHE     : {show: y, blk : 0, word: 6, pos : 9, len  : 1, start: 201, type      : bool, wr_dis  : 15, rd_dis: null, alt                            : '', dict             : '', desc: Disable flash cache in UART bootloader, rloc: 'EFUSE_BLK0_RDATA6_REG[9]', bloc: 'B25[1]'}
  KEY_STATUS           : {show: y, blk : 0, word: 6, pos: 10, len  : 1, start: 202, type      : bool, wr_dis  : 10, rd_dis   : 3, alt                            : '', dict             : '', desc: Usage of efuse block 3 (reserved), rloc: 'EFUSE_BLK0_RDATA6_REG[10]', bloc: 'B25[2]'}
  RESERVE_0_203        : {show: n, blk : 0, word: 6, pos: 11, len : 21, start: 203, type : 'uint:21', wr_dis: null, rd_dis: null, alt                            : '', dict             : '', desc: Reserved; it was created by set_missed_fields_in_regs func, rloc: 'EFUSE_BLK0_RDATA6_REG[31:11]', bloc: 'B25[7:3],B26,B27'}
  BLOCK1               : {show: y, blk : 1, word: 0, pos : 0, len: 256, start  : 0, type: 'bytes:32', wr_dis   : 7, rd_dis   : 0, alt             : ENCRYPT_FLASH_KEY, dict             : '', desc: Flash encryption key, rloc: EFUSE_BLK1_RDATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'}
  BLOCK2               : {show: y, blk : 2, word: 0, pos : 0, len: 256, start  : 0, type: 'bytes:32', wr_dis   : 8, rd_dis   : 1, alt               : SECURE_BOOT_KEY, dict             : '', desc: Security boot key, rloc: EFUSE_BLK2_RDATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'}
  CUSTOM_MAC_CRC       : {show: y, blk : 3, word: 0, pos : 0, len  : 8, start  : 0, type  : 'uint:8', wr_dis   : 9, rd_dis   : 2, alt                : MAC_CUSTOM_CRC, dict             : '', desc: CRC8 for custom MAC address, rloc: 'EFUSE_BLK3_RDATA0_REG[7:0]', bloc: B0}
  CUSTOM_MAC           : {show: y, blk : 3, word: 0, pos : 8, len : 48, start  : 8, type : 'bytes:6', wr_dis   : 9, rd_dis   : 2, alt                    : MAC_CUSTOM, dict             : '', desc: Custom MAC address, rloc: 'EFUSE_BLK3_RDATA0_REG[31:8]', bloc: 'B1,B2,B3,B4,B5,B6'}
  RESERVED_3_56        : {show: n, blk : 3, word: 1, pos: 24, len  : 8, start : 56, type  : 'uint:8', wr_dis   : 9, rd_dis   : 2, alt                            : '', dict             : '', desc: reserved, rloc: 'EFUSE_BLK3_RDATA1_REG[31:24]', bloc: B7}
  BLK3_RESERVED_2      : {show: n, blk : 3, word: 2, pos : 0, len : 32, start : 64, type : 'uint:32', wr_dis   : 9, rd_dis   : 2, alt                            : '', dict             : '', desc: read for BLOCK3, rloc: EFUSE_BLK3_RDATA2_REG, bloc: 'B8,B9,B10,B11'}
  ADC1_TP_LOW          : {show: y, blk : 3, word: 3, pos : 0, len  : 7, start : 96, type  : 'uint:7', wr_dis   : 9, rd_dis   : 2, alt                            : '', dict             : '', desc: ADC1 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE, rloc: 'EFUSE_BLK3_RDATA3_REG[6:0]', bloc: 'B12[6:0]'}
  ADC1_TP_HIGH         : {show: y, blk : 3, word: 3, pos : 7, len  : 9, start: 103, type  : 'uint:9', wr_dis   : 9, rd_dis   : 2, alt                            : '', dict             : '', desc: ADC1 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE, rloc: 'EFUSE_BLK3_RDATA3_REG[15:7]', bloc: 'B12[7],B13'}
  ADC2_TP_LOW          : {show: y, blk : 3, word: 3, pos: 16, len  : 7, start: 112, type  : 'uint:7', wr_dis   : 9, rd_dis   : 2, alt                            : '', dict             : '', desc: ADC2 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE, rloc: 'EFUSE_BLK3_RDATA3_REG[22:16]', bloc: 'B14[6:0]'}
  ADC2_TP_HIGH         : {show: y, blk : 3, word: 3, pos: 23, len  : 9, start: 119, type  : 'uint:9', wr_dis   : 9, rd_dis   : 2, alt                            : '', dict             : '', desc: ADC2 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE, rloc: 'EFUSE_BLK3_RDATA3_REG[31:23]', bloc: 'B14[7],B15'}
  SECURE_VERSION       : {show: y, blk : 3, word: 4, pos : 0, len : 32, start: 128, type : 'uint:32', wr_dis   : 9, rd_dis   : 2, alt                            : '', dict             : '', desc: Secure version for anti-rollback, rloc: EFUSE_BLK3_RDATA4_REG, bloc: 'B16,B17,B18,B19'}
  RESERVED_3_160       : {show: n, blk : 3, word: 5, pos : 0, len : 24, start: 160, type : 'uint:24', wr_dis   : 9, rd_dis   : 2, alt                            : '', dict             : '', desc: reserved, rloc: 'EFUSE_BLK3_RDATA5_REG[23:0]', bloc: 'B20,B21,B22'}
  MAC_VERSION          : {show: y, blk : 3, word: 5, pos: 24, len  : 8, start: 184, type  : 'uint:8', wr_dis   : 9, rd_dis   : 2, alt                : MAC_CUSTOM_VER, dict: '{1: "Custom MAC in BLOCK3"}', desc: Version of the MAC field, rloc: 'EFUSE_BLK3_RDATA5_REG[31:24]', bloc: B23}
  BLK3_RESERVED_6      : {show: n, blk : 3, word: 6, pos : 0, len : 32, start: 192, type : 'uint:32', wr_dis   : 9, rd_dis   : 2, alt                            : '', dict             : '', desc: read for BLOCK3, rloc: EFUSE_BLK3_RDATA6_REG, bloc: 'B24,B25,B26,B27'}
  BLK3_RESERVED_7      : {show: n, blk : 3, word: 7, pos : 0, len : 32, start: 224, type : 'uint:32', wr_dis   : 9, rd_dis   : 2, alt                            : '', dict             : '', desc: read for BLOCK3, rloc: EFUSE_BLK3_RDATA7_REG, bloc: 'B28,B29,B30,B31'}
