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<h1 id="awesome-hardware-description-languages">Awesome Hardware
Description Languages</h1>
<p>A curated list of amazingly awesome hardware description language
projects.</p>
<h1 id="hardware-development">Hardware development</h1>
<h2 id="hdl-doc">HDL doc</h2>
<ul>
<li>Verilog <a
href="https://inst.eecs.berkeley.edu/~cs150/fa06/Labs/verilog-ieee.pdf">IEEE
Std 1364-2001</a>, <a
href="http://sutherland-hdl.com/pdfs/verilog_2001_ref_guide.pdf">Quick
Ref Guide</a>, <a
href="http://www.ece.uah.edu/~gaede/cpe526/SystemVerilog_3.1a.pdf">SystemVerilog
3.1a</a>, <a
href="http://sutherland-hdl.com/papers/2013-SNUG-SV_Synthesizable-SystemVerilog_paper.pdf">Synthesizing
SystemVerilog Busting the Myth that SystemVerilog is only for
Verification</a></li>
<li>VHDL standards <a
href="http://edg.uchicago.edu/~tang/VHDLref.pdf">IEEE Std
1076-2000</a></li>
<li>SystemC standards <a
href="http://paginas.fe.up.pt/~ee07166/lib/exe/fetch.php?media=1666-2011.pdf">IEEE
Std 1666-2011</a></li>
</ul>
<h2 id="hdl-simulators-and-compilers">HDL simulators and compilers</h2>
<ul>
<li>Verilog
<ul>
<li><a href="https://www.veripool.org/wiki/verilator">Verilator</a>
Verilog to C++ transpiler</li>
<li><a href="http://iverilog.icarus.com/">Icarus Verilog</a> -
simulator</li>
<li><a href="http://www.clifford.at/yosys/">Yosys</a> - RTL
synthesis</li>
</ul></li>
<li>VHDL
<ul>
<li><a href="https://github.com/nickg/nvc">nvc</a> - GPLv3 VHDL compiler
and simulator, IEEE 1076-2002, written in C</li>
<li><a href="https://github.com/ghdl/ghdl">GHDL</a> - VHDL compiler and
simulator, IEEE 1076-2002, written in ADA</li>
</ul></li>
<li>chisel/firrtl
<ul>
<li><a href="https://github.com/ucsc-vama/essent">essent</a> - firrtl to
optimized C++ transpiler</li>
<li><a href="https://github.com/chipsalliance/treadle">treadle</a> -
firrtl simulator written in Scala</li>
</ul></li>
<li><a
href="https://inf.ethz.ch/personal/wirth/Lola/Lola2.pdf">Lola-2</a>
<ul>
<li><a href="https://inf.ethz.ch/personal/wirth/Lola/">Oberon-2013</a> -
Project Oberon, 2013 Edition, written in <a
href="http://www-oldurls.inf.ethz.ch/personal/wirth/Oberon/">Oberon-07</a>
<a
href="https://inf.ethz.ch/personal/wirth/ProjectOberon/license.txt">License</a></li>
</ul></li>
</ul>
<h2 id="meta-hdl-and-transpilers">Meta HDL and Transpilers</h2>
<ul>
<li>C++
<ul>
<li><a href="https://www.doulos.com/knowhow/systemc/">SystemC</a> - an
IEEE standard meta-HDL</li>
<li><a href="http://sysprogs.com/legacy/visualhdl/">VisualHDL</a> - an
integrated development environment (IDE) rapid design for FPGAs</li>
</ul></li>
<li>Dart
<ul>
<li><a href="https://github.com/intel/rohd">ROHD</a> - A framework for
hardware description and verification, 2021+</li>
</ul></li>
<li>Haskell
<ul>
<li><a href="https://github.com/conal/concat">concat</a> Haskell to
hardware, 2016+</li>
<li>https://github.com/conal/talk-2015-haskell-to-hardware</li>
<li><a href="https://github.com/clash-lang/clash-compiler">CλaSH</a> - A
functional hardware description language</li>
<li><a href="https://github.com/p12nGH/pipelineDSL">pipelineDSL</a> - A
Haskell DSL for describing hardware pipelines</li>
<li><a href="https://github.com/B-Lang-org/bsc">Bluespec</a> - Compiler,
simulator, and tools for the Bluespec Hardware Description
Language.</li>
<li><a href="https://github.com/zachjs/sv2v">sv2v</a> - SystemVerilog to
Verilog conversion</li>
</ul></li>
<li>Java
<ul>
<li><a href="http://www.jhdl.org/">jhdl</a> ..2006</li>
<li><a href="http://pshdl.org/">PSHDL</a></li>
</ul></li>
<li>JavaScript
<ul>
<li><a href="https://github.com/drom/reqack">reqack</a> - elastic
circuit toolchain</li>
<li><a href="https://github.com/DmitrySoshnikov/hdl-js">hdl-js</a> -
Hardware description language (HDL) parser, and Hardware simulator.</li>
<li><a href="https://github.com/jcbuisson/shdl">shdl</a> - Simple
Hardware Description Language</li>
</ul></li>
<li>Julia
<ul>
<li><a
href="https://github.com/interplanetary-robot/Verilog.jl">Julia-Verilog</a>
- a Verilog-generation DSL for Julia., 2017</li>
</ul></li>
<li>OCaml
<ul>
<li><a
href="https://github.com/janestreet/hardcaml/blob/master/docs/index.mdx">Hardcaml</a>
An OCaml library for designing hardware, complete with testing and
simulation tools.</li>
</ul></li>
<li>Kotlin
<ul>
<li><a href="https://github.com/frwang96/verik">Verik</a> HDL for design
and verification. generates SV. UVM.</li>
</ul></li>
<li>Python
<ul>
<li><a href="https://github.com/Nic30/hwt">HWT</a> Meta HDL,
verification env. IP-core generator, analysis tools, HDL glue</li>
<li><a href="https://github.com/StanfordAHA/garnet">garnet</a>
Coarse-Grained Reconfigurable Architecture generator based on magma,
2018+</li>
<li><a href="https://github.com/phanrahan/magma/">magma</a> - Meta HDL,
2017+</li>
<li><a href="https://github.com/m-labs/migen">migen</a> - Meta HDL,
2011+</li>
<li><a href="https://github.com/amaranth-lang/amaranth">Amaranth</a>
(previously nMigen) - A refreshed Python toolbox for building complex
digital hardware, 2018+</li>
<li><a href="https://github.com/myhdl/myhdl">MyHDL</a> - Process based
HDL, verification framework included, 2004+</li>
<li><a href="https://masc.soe.ucsc.edu/pyrope.html">Pyrope</a> -
Python-like language supporting “fluid pipelines” and “live flow”,
2017+</li>
<li><a href="https://github.com/UCSBarchlab/PyRTL">PyRTL</a> - Meta HDL,
simulator suitable for research.</li>
<li><a href="https://github.com/cornell-brg/pymtl">PyMTL</a> - Process
based HDL, verification framework included, 2014+</li>
<li><a href="https://github.com/PyHDI/veriloggen">veriloggen</a> -
Python, Verilog centric meta HDL with HLS like features, 2015-?</li>
<li><a href="https://github.com/dan-fritchman/Hdl21">Hdl21</a> - Analog
HDL in Python</li>
<li><a href="https://github.com/PyHGL/pyhgl">PyHGL</a> - Meta HDL,
three-state event-driven simulation, 2022+</li>
</ul></li>
<li>Ruby
<ul>
<li><a href="https://github.com/philtomson/RHDL">RHDL</a></li>
</ul></li>
<li>Rust
<ul>
<li><a href="https://github.com/tcr/hoodlum">hoodlum</a> - Meta HDL,
2016+</li>
<li><a href="https://github.com/yupferris/kaze">kaze</a> - Meta HDL,
2019+</li>
<li><a href="https://github.com/cucapra/calyx">calyx</a> - Intermediate
Language (IL) for Hardware Accelerator Generators, 2020+</li>
<li><a href="https://gitlab.com/spade-lang/spade">Spade</a> - A hardware
description language inspired by modern software languages like
Rust.</li>
</ul></li>
<li>Scala
<ul>
<li><a href="https://github.com/freechipsproject/chisel3">chisel</a> -
Meta HDL, 2012+</li>
<li><a href="https://github.com/SpinalHDL/SpinalHDL">SpinalHDL</a> -
Meta HDL 2012+</li>
</ul></li>
<li>C#
<ul>
<li><a href="https://github.com/EvgenyMuryshkin/qusoc">Quokka</a> - C#
to low-level RTL translator (Verilog, VHDL) and simulation toolkit
examples (gates, components, RISC-V, SoC)</li>
</ul></li>
<li>Veryl
<ul>
<li><a href="https://github.com/dalance/veryl">Veryl</a> - An original
HDL based on SystemVerilog / Rust syntax, and transplier to
SystemVerilog</li>
</ul></li>
</ul>
<h2 id="hls">HLS</h2>
<ul>
<li><a href="https://github.com/hlslibs">hlslibs</a> - ac_math, ac_dsp,
ac_types</li>
<li><a href="http://legup.eecg.utoronto.ca/">legup</a> - 2011-2015, LLVM
based c-&gt;verilog</li>
<li><a href="http://panda.dei.polimi.it/?page_id=31">bambu</a> - 2003-?,
GCC based c-&gt;verilog</li>
<li><a href="http://tima.imag.fr/sls/research-projects/augh/">augh</a> -
c-&gt;verilog, DSP support</li>
<li>https://github.com/utwente-fmt - abstract hls, verification
libraries</li>
<li><a href="https://github.com/etherzhhb/Shang">Shang</a> - 2012-2014,
LLVM based, c-&gt;verilog</li>
<li><a href="https://github.com/endrix/xronos">xronos</a> - 2012, java,
simple HLS</li>
<li><a href="https://github.com/SamuelBayliss/Potholes">Potholes</a> -
2012-2014 - polyhedral model preprocessor, Uses Vivado HLS, PET</li>
<li><a href="https://github.com/m8pple/hls_recurse">hls_recurse</a> -
2015-2016 - conversion of recursive fn. for stackless architectures</li>
<li><a href="https://github.com/funningboy/hg_lvl_syn">hg_lvl_syn</a> -
2010, ILP, Force Directed scheduler</li>
<li><a href="https://people.eecs.berkeley.edu/~alanmi/abc/">abc</a>
&lt;2008-?, A System for Sequential Synthesis and Verification</li>
<li><a href="https://github.com/ktok07b6/polyphony">polyphony</a> -
2015-2017, simple python to hdl</li>
<li><a href="https://github.com/ni/DelayGraph">DelayGraph</a> - 2016,
C#, register assignment algorithms</li>
<li><a href="https://github.com/dillonhuff/ahaHLS">ahaHLS</a> - 2019, An
open source high level synthesis (HLS) tool using LLVM</li>
<li><a
href="https://github.com/combinatorylogic/soc">combinatorylogic/soc</a>
- 2019, An experimental System-on-Chip with a custom compiler
toolchain.</li>
<li><a
href="https://github.com/EvgenyMuryshkin/QuokkaEvaluation">Quokka</a> -
C# to HL RTL translator</li>
<li><a href="https://github.com/Xilinx/HLS">Vitis</a> - LLVM based, made
by Xilinx. <a
href="https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_2/ug1399-vitis-hls.pdf">user
manual</a></li>
<li><a href="https://google.github.io/xls/">XLS</a> - 2020, HLS
toolchain from Google</li>
</ul>
<h2 id="other-hdl-languages">Other HDL languages</h2>
<ul>
<li><a href="https://github.com/asyncvlsi/act">act</a> - asynchronous
circuit/compiler tools</li>
<li><a href="https://github.com/google/autopiper">autopiper</a></li>
<li><a href="https://github.com/sylefeb/Silice">Silice</a> - A language
for hardcoding algorithms into FPGA hardware</li>
<li><a href="https://makerchip.com">TL-Verilog</a> - 2015+, Supports
“timing-abstract” and “transaction-level design” methodologies;
supported by proprietary and open-source tools</li>
</ul>
<h2 id="hardware-intermediate-representations">Hardware Intermediate
Representations</h2>
<ul>
<li><a href="https://circt.llvm.org">CIRCT</a> - 2020+, LLVM / MLIR
framework “Circuit IR Compilers and Tools”</li>
<li><a href="https://github.com/rdaly525/coreir">coreir</a> - 2016-?,
LLVM HW compiler## License</li>
<li><a href="https://github.com/masc-ucsc/lgraph">lgraph</a> - 2017-?, A
Multi-Language Synthesis and Simulation IR for Hardware Design</li>
<li><a href="https://github.com/freechipsproject/firrtl">firrtl</a> -
2016-?, Flexible Intermediate Representation for RTL</li>
<li><a href="https://github.com/fabianschuiki/llhd">LLHD</a> - Low Level
Hardware Description — A foundation for building hardware design
tools</li>
<li><a href="https://byuccl.github.io/spydrnet/">SpyDrNet</a> - 2019+,
Framework for parsing and manipulating structural netlists in
Python</li>
<li><a href="https://github.com/Vlsir/Vlsir">VLSIR</a> - IC Interchange
Formats, defined in Google Protobuf SDL</li>
</ul>
<h2 id="synthesis-tools">Synthesis tools</h2>
<ul>
<li><a
href="https://github.com/verilog-to-routing/vtr-verilog-to-routing">vtr-verilog-to-routing</a></li>
<li><a href="https://github.com/YosysHQ/yosys">yosys</a> - RTL synthesis
framework</li>
</ul>
<h2 id="visualization-and-documentation-generators">Visualization and
Documentation generators</h2>
<ul>
<li><a href="https://github.com/drom/bitfield">bitfield</a> - Javascript
bit field diagram renderer</li>
<li><a href="https://github.com/Nic30/d3-wave">d3-wave</a> - Javascript
wave graph visualizer for RTL simulations</li>
<li><a href="https://github.com/Nic30/d3-hwschematic">d3-hwschematic</a>
- Javascript hierarchical schematic visualizer for HDLs</li>
<li><a href="https://github.com/drom/wavedrom">wavedrom</a> - Javascript
wave graph visualizer for documentations and sim.</li>
<li><a href="https://github.com/nturley/netlistsvg">netlistsvg</a> -
Javascript schematic visualizer</li>
<li><a href="https://github.com/Nic30/sphinx-hwt">sphinx-hwt</a> -
Plugin for sphinx documentation generator which adds schematic into html
documentation.</li>
<li><a href="https://redwoodeda.com/viz">Visual Debug</a> - Custom
simulation visualization framework, available within the <a
href="https://makerchip.com">Makerchip.com</a> IDE.</li>
</ul>
<h2 id="hdl-parsers">HDL parsers</h2>
<ul>
<li><a href="https://github.com/Nic30/hdlConvertor">hdlConvertor</a> -
Fast (System) Verilog/VHDL parser written as C++ extension for
Python</li>
<li><a href="https://github.com/Paebbels/pyVHDLParser">pyVHDLParser</a>
- VHDL parser written in Python</li>
<li><a href="https://github.com/kraigher/rust_hdl">rust_hdl</a> - VHDL
parser and language server written in Rust</li>
<li><a href="https://github.com/dalance/sv-parser">sv-parser</a> - IEEE
1800-2017 System Verilog Parser written in Rust</li>
<li><a href="https://chipsalliance.github.io/verible/">verible</a> -
Verible provides a SystemVerilog parser, style-linter, and
formatter.</li>
<li><a href="https://github.com/MikePopoloski/slang">slang</a> -
SystemVerilog compiler and language service.</li>
<li><a href="https://github.com/PyHDI/Pyverilog">pyverilog</a> -
Python-based Hardware Design Processing Toolkit for Verilog HDL</li>
<li><a href="https://github.com/chipsalliance/Surelog">Surelog</a> -
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler.
Provides IEEE Design/TB C/C++ VPI and Python AST API.</li>
</ul>
<h2 id="other-simulation-tools">Other Simulation tools</h2>
<ul>
<li><a href="https://github.com/ucb-bar/midas">midas</a> -
FPGA-Accelerated Simulation Framework Automatically Transforming
Arbitrary RTL</li>
<li><a href="https://github.com/potentialventures/cocotb">cocotb</a> - A
coroutine based co-simulation library for writing VHDL and Verilog
testbenches in Python</li>
<li><a href="https://github.com/OSVVM/OsvvmLibraries">osvvm</a> - A VHDL
verification framework, verification utility library, verification
component library, and a simulator independent scripting flow</li>
<li><a href="https://github.com/OSVVM/OsvvmLibraries">uvvm</a> - A free
and Open Source Methodology and Library for VHDL verification of FPGA
and ASIC.</li>
</ul>
<h2 id="other-design-automation-tools">Other Design Automation
tools</h2>
<ul>
<li><a href="https://github.com/SystemRDL/PeakRDL">peakrdl</a> - CSR
toolchain to generate RTL, UVM RAL models, docment(html and markdown),
IPXACT, c header from SystemRDL or IPXACT.</li>
<li><a href="https://github.com/rggen/rggen">RgGen</a> - Code generator
tool to generate RTL, UVM RAL models and Wiki documents from CSR
specifications</li>
<li><a href="https://symbiflow.github.io/sv-tests">sv-tests</a> - Test
suite designed to check compliance with the SystemVerilog standard</li>
<li><a href="https://github.com/prasadp4009/tbengy">tbengy</a> - Code
generator tool to generate SV/UVM RTL and Testbech as well scripts with
support for bitstream generation for Digilent FPGAs</li>
<li><a href="https://github.com/WilsonChen003/HDLGen">HDLGen</a> - Tool
for processing of embedded Perl or Python scripts in Verilog source
code.</li>
<li><a href="https://github.com/olofk/fusesoc">fusesoc</a> - Package
manager and a set of build tools for HDL.</li>
<li><a href="https://github.com/pulp-platform/bender">bender</a> -
Dependency management tool for hardware design projects.</li>
<li><a href="https://github.com/m-kru/hbs">hbs</a> - A lean dependency
management and build system for hardware description projects.</li>
</ul>
<h2 id="license">License</h2>
<p><a href="https://creativecommons.org/publicdomain/zero/1.0/"><img
src="http://mirrors.creativecommons.org/presskit/buttons/88x31/svg/cc-zero.svg"
alt="CC0" /></a></p>
<p>To the extent possible under law, <a href="http://drom.io">Aliaksei
Chapyzhenka</a> has waived all copyright and related or neighboring
rights to this work.</p>
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