Awesome Hardware
Description Languages
A curated list of amazingly awesome hardware description language
projects.
Hardware development
HDL doc
HDL simulators and compilers
- Verilog
- VHDL
- nvc - GPLv3 VHDL compiler
and simulator, IEEE 1076-2002, written in C
- GHDL - VHDL compiler and
simulator, IEEE 1076-2002, written in ADA
- chisel/firrtl
- essent - firrtl to
optimized C++ transpiler
- treadle -
firrtl simulator written in Scala
- Lola-2
- CIRCT
- ksim - CIRCT IR to
optimized C++ transpiler
- arcilator - Fast
and cycle-accurate hardware simulation in CIRCT
- C++
- SystemC - an
IEEE standard meta-HDL
- VisualHDL - an
integrated development environment (IDE) rapid design for FPGAs
- Dart
- ROHD - A framework for
hardware description and verification, 2021+
- Haskell
- concat Haskell to
hardware, 2016+
- https://github.com/conal/talk-2015-haskell-to-hardware
- CλaSH - A
functional hardware description language
- pipelineDSL - A
Haskell DSL for describing hardware pipelines
- Bluespec - Compiler,
simulator, and tools for the Bluespec Hardware Description
Language.
- sv2v - SystemVerilog to
Verilog conversion
- Java
- JavaScript
- reqack - elastic
circuit toolchain
- hdl-js -
Hardware description language (HDL) parser, and Hardware simulator.
- shdl - Simple
Hardware Description Language
- Julia
- OCaml
- Hardcaml
An OCaml library for designing hardware, complete with testing and
simulation tools.
- Kotlin
- Verik HDL for design
and verification. generates SV. UVM.
- Python
- HWT Meta HDL,
verification env. IP-core generator, analysis tools, HDL glue
- garnet
Coarse-Grained Reconfigurable Architecture generator based on magma,
2018+
- magma - Meta HDL,
2017+
- migen - Meta HDL,
2011+
- Amaranth
(previously nMigen) - A refreshed Python toolbox for building complex
digital hardware, 2018+
- MyHDL - Process based
HDL, verification framework included, 2004+
- Pyrope -
Python-like language supporting “fluid pipelines” and “live flow”,
2017+
- PyRTL - Meta HDL,
simulator suitable for research.
- PyMTL - Process
based HDL, verification framework included, 2014+
- veriloggen -
Python, Verilog centric meta HDL with HLS like features, 2015-?
- Hdl21 - Analog
HDL in Python
- PyHGL - Meta HDL,
three-state event-driven simulation, 2022+
- GateForge - Meta
HDL, 2025+
- Ruby
- Rust
- hoodlum - Meta HDL,
2016+
- kaze - Meta HDL,
2019+
- calyx - Intermediate
Language (IL) for Hardware Accelerator Generators, 2020+
- Spade - A hardware
description language inspired by modern software languages like
Rust.
- Cement - A
rule-based Meta HDL inspired by Bluespec, 2024+
- Scala
- C#
- Quokka - C#
to low-level RTL translator (Verilog, VHDL) and simulation toolkit
examples (gates, components, RISC-V, SoC)
- Veryl
- Veryl - An original
HDL based on SystemVerilog / Rust syntax, and transplier to
SystemVerilog
HLS
- hlslibs - ac_math, ac_dsp,
ac_types
- legup - 2011-2015, LLVM
based c->verilog
- bambu - 2003-?,
GCC based c->verilog
- augh -
c->verilog, DSP support
- https://github.com/utwente-fmt - abstract hls, verification
libraries
- Shang - 2012-2014,
LLVM based, c->verilog
- xronos - 2012, java,
simple HLS
- Potholes -
2012-2014 - polyhedral model preprocessor, Uses Vivado HLS, PET
- hls_recurse -
2015-2016 - conversion of recursive fn. for stackless architectures
- hg_lvl_syn -
2010, ILP, Force Directed scheduler
- abc
<2008-?, A System for Sequential Synthesis and Verification
- polyphony -
2015-2017, simple python to hdl
- DelayGraph - 2016,
C#, register assignment algorithms
- ahaHLS - 2019, An
open source high level synthesis (HLS) tool using LLVM
- combinatorylogic/soc
- 2019, An experimental System-on-Chip with a custom compiler
toolchain.
- Quokka -
C# to HL RTL translator
- Vitis - LLVM based, made
by Xilinx. user
manual
- XLS - 2020, HLS
toolchain from Google
- hector - 2022, An
open-source hardware synthesis framework using MLIR
Other HDL languages
- act - asynchronous
circuit/compiler tools
- autopiper
- Silice - A language
for hardcoding algorithms into FPGA hardware
- TL-Verilog - 2015+, Supports
“timing-abstract” and “transaction-level design” methodologies;
supported by proprietary and open-source tools
- CIRCT - 2020+, LLVM / MLIR
framework “Circuit IR Compilers and Tools”
- coreir - 2016-?,
LLVM HW compiler## License
- lgraph - 2017-?, A
Multi-Language Synthesis and Simulation IR for Hardware Design
- firrtl -
2016-?, Flexible Intermediate Representation for RTL
- LLHD - Low Level
Hardware Description — A foundation for building hardware design
tools
- SpyDrNet - 2019+,
Framework for parsing and manipulating structural netlists in
Python
- VLSIR - IC Interchange
Formats, defined in Google Protobuf SDL
Visualization and
Documentation generators
- bitfield - Javascript
bit field diagram renderer
- d3-wave - Javascript
wave graph visualizer for RTL simulations
- d3-hwschematic
- Javascript hierarchical schematic visualizer for HDLs
- wavedrom - Javascript
wave graph visualizer for documentations and sim.
- netlistsvg -
Javascript schematic visualizer
- sphinx-hwt -
Plugin for sphinx documentation generator which adds schematic into html
documentation.
- Visual Debug - Custom
simulation visualization framework, available within the Makerchip.com IDE.
HDL parsers
- hdlConvertor -
Fast (System) Verilog/VHDL parser written as C++ extension for
Python
- pyVHDLParser
- VHDL parser written in Python
- rust_hdl - VHDL
parser and language server written in Rust
- sv-parser - IEEE
1800-2017 System Verilog Parser written in Rust
- verible -
Verible provides a SystemVerilog parser, style-linter, and
formatter.
- slang -
SystemVerilog compiler and language service.
- pyverilog -
Python-based Hardware Design Processing Toolkit for Verilog HDL
- Surelog -
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler.
Provides IEEE Design/TB C/C++ VPI and Python AST API.
- midas -
FPGA-Accelerated Simulation Framework Automatically Transforming
Arbitrary RTL
- cocotb - A
coroutine based co-simulation library for writing VHDL and Verilog
testbenches in Python
- osvvm - A VHDL
verification framework, verification utility library, verification
component library, and a simulator independent scripting flow
- uvvm - A free
and Open Source Methodology and Library for VHDL verification of FPGA
and ASIC.
- crave - Constrained
random stimuli generation for C++ and SystemC (AntMicro’s fork of crave)
- peakrdl - CSR
toolchain to generate RTL, UVM RAL models, document(html and markdown),
IPXACT, c header from SystemRDL or IPXACT.
- RgGen - Code generator
tool to generate RTL, UVM RAL models and Wiki documents from CSR
specifications
- sv-tests - Test
suite designed to check compliance with the SystemVerilog standard
- tbengy - Code
generator tool to generate SV/UVM RTL and Testbech as well scripts with
support for bitstream generation for Digilent FPGAs
- HDLGen - Tool
for processing of embedded Perl or Python scripts in Verilog source
code.
- fusesoc - Package
manager and a set of build tools for HDL.
- bender -
Dependency management tool for hardware design projects.
- hbs - A lean dependency
management and build system for hardware description projects.
- svlint -
SystemVerilog linter compliant with IEEE1800-2017. Written in Rust,
based on sv-parser.
PSS : Portable test and
Stimulus Standard
License
To the extent possible under law, Aliaksei
Chapyzhenka has waived all copyright and related or neighboring
rights to this work.
hdl.md Github