Update and add index
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terminal/hdl
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terminal/hdl
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[38;5;12m [39m[38;2;255;187;0m[1m[4mAwesome Hardware Description Languages[0m
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[38;5;12m [39m[38;2;255;187;0m[1m[4mAwesome Hardware Description Languages[0m
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[38;5;12mA curated list of amazingly awesome hardware description language projects.[39m
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[38;5;12m [39m[38;2;255;187;0m[1m[4mHardware development[0m
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[38;5;12m [39m[38;2;255;187;0m[1m[4mHardware development[0m
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[38;2;255;187;0m[4mHDL doc[0m
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[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;12mVerilog[39m[38;5;12m [39m[38;5;14m[1mIEEE[0m[38;5;14m[1m [0m[38;5;14m[1mStd[0m[38;5;14m[1m [0m[38;5;14m[1m1364-2001[0m[38;5;12m [39m[38;5;12m(https://inst.eecs.berkeley.edu/~cs150/fa06/Labs/verilog-ieee.pdf),[39m[38;5;12m [39m[38;5;14m[1mQuick[0m[38;5;14m[1m [0m[38;5;14m[1mRef[0m[38;5;14m[1m [0m[38;5;14m[1mGuide[0m[38;5;12m [39m[38;5;12m(http://sutherland-hdl.com/pdfs/verilog_2001_ref_guide.pdf),[39m[38;5;12m [39m[38;5;14m[1mSystemVerilog[0m[38;5;14m[1m [0m
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[38;5;14m[1m3.1a[0m[38;5;12m [39m[38;5;12m(http://www.ece.uah.edu/~gaede/cpe526/SystemVerilog_3.1a.pdf),[39m[38;5;12m [39m[38;5;14m[1mSynthesizing[0m[38;5;14m[1m [0m[38;5;14m[1mSystemVerilog[0m[38;5;14m[1m [0m[38;5;14m[1mBusting[0m[38;5;14m[1m [0m[38;5;14m[1mthe[0m[38;5;14m[1m [0m[38;5;14m[1mMyth[0m[38;5;14m[1m [0m[38;5;14m[1mthat[0m[38;5;14m[1m [0m[38;5;14m[1mSystemVerilog[0m[38;5;14m[1m [0m[38;5;14m[1mis[0m[38;5;14m[1m [0m[38;5;14m[1monly[0m[38;5;14m[1m [0m[38;5;14m[1mfor[0m[38;5;14m[1m [0m[38;5;14m[1mVerification[0m[38;5;12m [39m
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[38;5;12m(http://sutherland-hdl.com/papers/2013-SNUG-SV_Synthesizable-SystemVerilog_paper.pdf)[39m
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[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;12mVerilog[39m[38;5;12m [39m[38;5;14m[1mIEEE[0m[38;5;14m[1m [0m[38;5;14m[1mStd[0m[38;5;14m[1m [0m[38;5;14m[1m1364-2001[0m[38;5;12m [39m[38;5;12m(https://inst.eecs.berkeley.edu/~cs150/fa06/Labs/verilog-ieee.pdf),[39m[38;5;12m [39m[38;5;14m[1mQuick[0m[38;5;14m[1m [0m[38;5;14m[1mRef[0m[38;5;14m[1m [0m[38;5;14m[1mGuide[0m[38;5;12m [39m[38;5;12m(http://sutherland-hdl.com/pdfs/verilog_2001_ref_guide.pdf),[39m[38;5;12m [39m[38;5;14m[1mSystemVerilog[0m[38;5;14m[1m [0m[38;5;14m[1m3.1a[0m[38;5;12m [39m
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[38;5;12m(http://www.ece.uah.edu/~gaede/cpe526/SystemVerilog_3.1a.pdf),[39m[38;5;12m [39m[38;5;14m[1mSynthesizing[0m[38;5;14m[1m [0m[38;5;14m[1mSystemVerilog[0m[38;5;14m[1m [0m[38;5;14m[1mBusting[0m[38;5;14m[1m [0m[38;5;14m[1mthe[0m[38;5;14m[1m [0m[38;5;14m[1mMyth[0m[38;5;14m[1m [0m[38;5;14m[1mthat[0m[38;5;14m[1m [0m[38;5;14m[1mSystemVerilog[0m[38;5;14m[1m [0m[38;5;14m[1mis[0m[38;5;14m[1m [0m[38;5;14m[1monly[0m[38;5;14m[1m [0m[38;5;14m[1mfor[0m[38;5;14m[1m [0m[38;5;14m[1mVerification[0m[38;5;12m [39m[38;5;12m(http://sutherland-hdl.com/papers/2013-SNUG-SV_Synthesizable-SystemVerilog_paper.pdf)[39m
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[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;12mVHDL standards [39m[38;5;14m[1mIEEE Std 1076-2000[0m[38;5;12m (http://edg.uchicago.edu/~tang/VHDLref.pdf)[39m
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[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;12mSystemC standards [39m[38;5;14m[1mIEEE Std 1666-2011[0m[38;5;12m (http://paginas.fe.up.pt/~ee07166/lib/exe/fetch.php?media=1666-2011.pdf)[39m
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@@ -27,8 +26,8 @@
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[48;5;235m[38;5;249m * **essent** (https://github.com/ucsc-vama/essent) - firrtl to optimized C++ transpiler[49m[39m[48;5;235m[38;5;249m [49m[39m
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[48;5;235m[38;5;249m * **treadle** (https://github.com/chipsalliance/treadle) - firrtl simulator written in Scala[49m[39m
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[38;5;12m [39m[38;5;12m [39m[38;5;12m [39m[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;14m[1mLola-2[0m[38;5;12m (https://inf.ethz.ch/personal/wirth/Lola/Lola2.pdf)[39m
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[48;5;235m[38;5;249m - **Oberon-2013** (https://inf.ethz.ch/personal/wirth/Lola/) - Project Oberon, 2013 Edition, written in **Oberon-07** (http://www-oldurls.inf.ethz.ch/personal/wirth/Oberon/) **License** (ht[49m[39m[48;5;235m[38;5;249m [49m[39m
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[48;5;235m[38;5;249mtps://inf.ethz.ch/personal/wirth/ProjectOberon/license.txt)[49m[39m[48;5;235m[38;5;249m [49m[39m
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[48;5;235m[38;5;249m - **Oberon-2013** (https://inf.ethz.ch/personal/wirth/Lola/) - Project Oberon, 2013 Edition, written in **Oberon-07** (http://www-oldurls.inf.ethz.ch/personal/wirth/Oberon/) **License** (https://inf.ethz.ch/personal/wirth/ProjectObero[49m[39m[48;5;235m[38;5;249m [49m[39m
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[48;5;235m[38;5;249mn/license.txt)[49m[39m[48;5;235m[38;5;249m [49m[39m
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[38;2;255;187;0m[4mMeta HDL and Transpilers[0m
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