[38;5;12m                                                                                                   [39m[38;2;255;187;0m[1m[4mAwesome Hardware Description Languages[0m

[38;5;12mA curated list of amazingly awesome hardware description language projects.[39m


[38;5;12m                                                                                                            [39m[38;2;255;187;0m[1m[4mHardware development[0m

[38;2;255;187;0m[4mHDL doc[0m

[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;12mVerilog[39m[38;5;12m [39m[38;5;14m[1mIEEE[0m[38;5;14m[1m [0m[38;5;14m[1mStd[0m[38;5;14m[1m [0m[38;5;14m[1m1364-2001[0m[38;5;12m [39m[38;5;12m(https://inst.eecs.berkeley.edu/~cs150/fa06/Labs/verilog-ieee.pdf),[39m[38;5;12m [39m[38;5;14m[1mQuick[0m[38;5;14m[1m [0m[38;5;14m[1mRef[0m[38;5;14m[1m [0m[38;5;14m[1mGuide[0m[38;5;12m [39m[38;5;12m(http://sutherland-hdl.com/pdfs/verilog_2001_ref_guide.pdf),[39m[38;5;12m [39m[38;5;14m[1mSystemVerilog[0m[38;5;14m[1m [0m[38;5;14m[1m3.1a[0m[38;5;12m [39m
[38;5;12m(http://www.ece.uah.edu/~gaede/cpe526/SystemVerilog_3.1a.pdf),[39m[38;5;12m [39m[38;5;14m[1mSynthesizing[0m[38;5;14m[1m [0m[38;5;14m[1mSystemVerilog[0m[38;5;14m[1m [0m[38;5;14m[1mBusting[0m[38;5;14m[1m [0m[38;5;14m[1mthe[0m[38;5;14m[1m [0m[38;5;14m[1mMyth[0m[38;5;14m[1m [0m[38;5;14m[1mthat[0m[38;5;14m[1m [0m[38;5;14m[1mSystemVerilog[0m[38;5;14m[1m [0m[38;5;14m[1mis[0m[38;5;14m[1m [0m[38;5;14m[1monly[0m[38;5;14m[1m [0m[38;5;14m[1mfor[0m[38;5;14m[1m [0m[38;5;14m[1mVerification[0m[38;5;12m [39m[38;5;12m(http://sutherland-hdl.com/papers/2013-SNUG-SV_Synthesizable-SystemVerilog_paper.pdf)[39m
[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;12mVHDL standards [39m[38;5;14m[1mIEEE Std 1076-2000[0m[38;5;12m (http://edg.uchicago.edu/~tang/VHDLref.pdf)[39m
[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;12mSystemC standards [39m[38;5;14m[1mIEEE Std 1666-2011[0m[38;5;12m (http://paginas.fe.up.pt/~ee07166/lib/exe/fetch.php?media=1666-2011.pdf)[39m


[38;2;255;187;0m[4mHDL simulators and compilers[0m

[38;5;12m [39m[38;5;12m [39m[38;5;12m [39m[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;12mVerilog[39m
[48;5;235m[38;5;249m  - **Verilator** (https://www.veripool.org/wiki/verilator) Verilog to C++ transpiler[49m[39m
[48;5;235m[38;5;249m  - **Icarus Verilog** (http://iverilog.icarus.com/) - simulator[49m[39m[48;5;235m[38;5;249m                     [49m[39m
[48;5;235m[38;5;249m  - **Yosys** (http://www.clifford.at/yosys/) - RTL synthesis[49m[39m[48;5;235m[38;5;249m                        [49m[39m
[38;5;12m [39m[38;5;12m [39m[38;5;12m [39m[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;12mVHDL[39m
[48;5;235m[38;5;249m  * **nvc** (https://github.com/nickg/nvc) - GPLv3 VHDL compiler and simulator, IEEE 1076-2002, written in C[49m[39m
[48;5;235m[38;5;249m  * **GHDL** (https://github.com/ghdl/ghdl) - VHDL compiler and simulator, IEEE 1076-2002, written in ADA[49m[39m[48;5;235m[38;5;249m   [49m[39m
[38;5;12m [39m[38;5;12m [39m[38;5;12m [39m[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;12mchisel/firrtl[39m
[48;5;235m[38;5;249m  * **essent** (https://github.com/ucsc-vama/essent) - firrtl to optimized C++ transpiler[49m[39m[48;5;235m[38;5;249m     [49m[39m
[48;5;235m[38;5;249m  * **treadle** (https://github.com/chipsalliance/treadle) - firrtl simulator written in Scala[49m[39m
[38;5;12m [39m[38;5;12m [39m[38;5;12m [39m[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;14m[1mLola-2[0m[38;5;12m (https://inf.ethz.ch/personal/wirth/Lola/Lola2.pdf)[39m
[48;5;235m[38;5;249m  - **Oberon-2013** (https://inf.ethz.ch/personal/wirth/Lola/) - Project Oberon, 2013 Edition, written in **Oberon-07** (http://www-oldurls.inf.ethz.ch/personal/wirth/Oberon/) **License** (https://inf.ethz.ch/personal/wirth/ProjectObero[49m[39m[48;5;235m[38;5;249m              [49m[39m
[48;5;235m[38;5;249mn/license.txt)[49m[39m[48;5;235m[38;5;249m                                                                                                                                                                                                                                            [49m[39m


[38;2;255;187;0m[4mMeta HDL and Transpilers[0m

[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;12mC++[39m
[38;5;12m   - [39m[38;5;14m[1mSystemC[0m[38;5;12m (https://www.doulos.com/knowhow/systemc/) - an IEEE standard meta-HDL[39m
[38;5;12m   - [39m[38;5;14m[1mVisualHDL[0m[38;5;12m (http://sysprogs.com/legacy/visualhdl/) - an integrated development environment (IDE) rapid design for FPGAs[39m

[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;12mDart[39m
[38;5;12m   - [39m[38;5;14m[1mROHD[0m[38;5;12m (https://github.com/intel/rohd) - A framework for hardware description and verification, 2021+[39m

[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;12mHaskell[39m
[38;5;12m   - [39m[38;5;14m[1mconcat[0m[38;5;12m (https://github.com/conal/concat) Haskell to hardware, 2016+[39m
[38;5;12m   - https://github.com/conal/talk-2015-haskell-to-hardware[39m
[38;5;12m   - [39m[38;5;14m[1mCλaSH[0m[38;5;12m (https://github.com/clash-lang/clash-compiler) - A functional hardware description language[39m
[38;5;12m   - [39m[38;5;14m[1mpipelineDSL[0m[38;5;12m (https://github.com/p12nGH/pipelineDSL) - A Haskell DSL for describing hardware pipelines[39m
[38;5;12m   - [39m[38;5;14m[1mBluespec[0m[38;5;12m (https://github.com/B-Lang-org/bsc) - Compiler, simulator, and tools for the Bluespec Hardware Description Language.[39m
[38;5;12m   - [39m[38;5;14m[1msv2v[0m[38;5;12m (https://github.com/zachjs/sv2v) - SystemVerilog to Verilog conversion[39m

[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;12mJava[39m
[38;5;12m   - [39m[38;5;14m[1mjhdl[0m[38;5;12m (http://www.jhdl.org/) ..2006[39m
[38;5;12m   - [39m[38;5;14m[1mPSHDL[0m[38;5;12m (http://pshdl.org/)[39m

[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;12mJavaScript[39m
[38;5;12m   - [39m[38;5;14m[1mreqack[0m[38;5;12m (https://github.com/drom/reqack) -  elastic circuit toolchain[39m
[38;5;12m   - [39m[38;5;14m[1mhdl-js[0m[38;5;12m (https://github.com/DmitrySoshnikov/hdl-js) - Hardware description language (HDL) parser, and Hardware simulator.[39m
[38;5;12m   - [39m[38;5;14m[1mshdl[0m[38;5;12m (https://github.com/jcbuisson/shdl) - Simple Hardware Description Language[39m

[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;12mJulia[39m
[38;5;12m   - [39m[38;5;14m[1mJulia-Verilog[0m[38;5;12m (https://github.com/interplanetary-robot/Verilog.jl) - a Verilog-generation DSL for Julia., 2017[39m

[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;12mOCaml[39m
[38;5;12m   - [39m[38;5;14m[1mHardcaml[0m[38;5;12m (https://github.com/janestreet/hardcaml/blob/master/docs/index.mdx) An OCaml library for designing hardware, complete with testing and simulation tools.[39m

[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;12mKotlin[39m
[38;5;12m  - [39m[38;5;14m[1mVerik[0m[38;5;12m (https://github.com/frwang96/verik) HDL for design and verification. generates SV. UVM.[39m

[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;12mPython[39m
[38;5;12m  - [39m[38;5;14m[1mHWT[0m[38;5;12m (https://github.com/Nic30/hwt) Meta HDL, verification env. IP-core generator, analysis tools, HDL glue[39m
[38;5;12m  - [39m[38;5;14m[1mgarnet[0m[38;5;12m (https://github.com/StanfordAHA/garnet) Coarse-Grained Reconfigurable Architecture generator based on magma, 2018+[39m
[38;5;12m  - [39m[38;5;14m[1mmagma[0m[38;5;12m (https://github.com/phanrahan/magma/) - Meta HDL, 2017+[39m
[38;5;12m  - [39m[38;5;14m[1mmigen[0m[38;5;12m (https://github.com/m-labs/migen) - Meta HDL, 2011+[39m
[38;5;12m  - [39m[38;5;14m[1mAmaranth[0m[38;5;12m (https://github.com/amaranth-lang/amaranth) (previously nMigen) - A refreshed Python toolbox for building complex digital hardware, 2018+[39m
[38;5;12m  - [39m[38;5;14m[1mMyHDL[0m[38;5;12m (https://github.com/myhdl/myhdl) - Process based HDL, verification framework included, 2004+[39m
[38;5;12m  - [39m[38;5;14m[1mPyrope[0m[38;5;12m (https://masc.soe.ucsc.edu/pyrope.html) - Python-like language supporting "fluid pipelines" and "live flow", 2017+[39m
[38;5;12m  - [39m[38;5;14m[1mPyRTL[0m[38;5;12m (https://github.com/UCSBarchlab/PyRTL) - Meta HDL, simulator suitable for research.[39m
[38;5;12m  - [39m[38;5;14m[1mPyMTL[0m[38;5;12m (https://github.com/cornell-brg/pymtl) - Process based HDL, verification framework included, 2014+[39m
[38;5;12m  - [39m[38;5;14m[1mveriloggen[0m[38;5;12m (https://github.com/PyHDI/veriloggen) - Python, Verilog centric meta HDL with HLS like features, 2015-?[39m
[38;5;12m  - [39m[38;5;14m[1mHdl21[0m[38;5;12m (https://github.com/dan-fritchman/Hdl21) - Analog HDL in Python[39m
[38;5;12m  - [39m[38;5;14m[1mPyHGL[0m[38;5;12m (https://github.com/PyHGL/pyhgl) - Meta HDL, three-state event-driven simulation, 2022+[39m

[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;12mRuby[39m
[38;5;12m   - [39m[38;5;14m[1mRHDL[0m[38;5;12m (https://github.com/philtomson/RHDL)[39m

[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;12mRust[39m
[38;5;12m   - [39m[38;5;14m[1mhoodlum[0m[38;5;12m (https://github.com/tcr/hoodlum) - Meta HDL, 2016+[39m
[38;5;12m   - [39m[38;5;14m[1mkaze[0m[38;5;12m (https://github.com/yupferris/kaze) - Meta HDL, 2019+[39m
[38;5;12m   - [39m[38;5;14m[1mcalyx[0m[38;5;12m (https://github.com/cucapra/calyx) - Intermediate Language (IL) for Hardware Accelerator Generators, 2020+[39m
[38;5;12m   - [39m[38;5;14m[1mSpade[0m[38;5;12m (https://gitlab.com/spade-lang/spade) - A hardware description language inspired by modern software languages like Rust.[39m

[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;12mScala[39m
[38;5;12m   - [39m[38;5;14m[1mchisel[0m[38;5;12m (https://github.com/freechipsproject/chisel3) - Meta HDL, 2012+[39m
[38;5;12m   - [39m[38;5;14m[1mSpinalHDL[0m[38;5;12m (https://github.com/SpinalHDL/SpinalHDL) - Meta HDL 2012+[39m

[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;12mC#[39m
[38;5;12m   - [39m[38;5;14m[1mQuokka[0m[38;5;12m (https://github.com/EvgenyMuryshkin/qusoc) - C# to low-level RTL translator (Verilog, VHDL) and simulation toolkit examples (gates, components, RISC-V, SoC) [39m

[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;12mVeryl[39m
[38;5;12m   - [39m[38;5;14m[1mVeryl[0m[38;5;12m (https://github.com/dalance/veryl) - An original HDL based on SystemVerilog / Rust syntax, and transplier to SystemVerilog[39m
[48;5;235m[38;5;249m[49m[39m
[38;2;255;187;0m[4mHLS[0m

[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;14m[1mhlslibs[0m[38;5;12m (https://github.com/hlslibs) - ac_math, ac_dsp, ac_types[39m
[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;14m[1mlegup[0m[38;5;12m (http://legup.eecg.utoronto.ca/) - 2011-2015, LLVM based c->verilog[39m
[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;14m[1mbambu[0m[38;5;12m (http://panda.dei.polimi.it/?page_id=31) - 2003-?, GCC based c->verilog[39m
[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;14m[1maugh[0m[38;5;12m (http://tima.imag.fr/sls/research-projects/augh/) - c->verilog, DSP support[39m
[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;12mhttps://github.com/utwente-fmt - abstract hls, verification libraries[39m
[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;14m[1mShang[0m[38;5;12m (https://github.com/etherzhhb/Shang) - 2012-2014, LLVM based, c->verilog[39m
[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;14m[1mxronos[0m[38;5;12m (https://github.com/endrix/xronos) - 2012, java, simple HLS[39m
[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;14m[1mPotholes[0m[38;5;12m (https://github.com/SamuelBayliss/Potholes) - 2012-2014 - polyhedral model preprocessor, Uses Vivado HLS, PET[39m
[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;14m[1mhls_recurse[0m[38;5;12m (https://github.com/m8pple/hls_recurse) - 2015-2016 - conversion of recursive fn. for stackless architectures[39m
[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;14m[1mhg_lvl_syn[0m[38;5;12m (https://github.com/funningboy/hg_lvl_syn) - 2010, ILP, Force Directed scheduler[39m
[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;14m[1mabc[0m[38;5;12m (https://people.eecs.berkeley.edu/~alanmi/abc/) <2008-?, A System for Sequential Synthesis and Verification[39m
[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;14m[1mpolyphony[0m[38;5;12m (https://github.com/ktok07b6/polyphony) - 2015-2017, simple python to hdl[39m
[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;14m[1mDelayGraph[0m[38;5;12m (https://github.com/ni/DelayGraph) - 2016, C#, register assignment algorithms[39m
[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;14m[1mahaHLS[0m[38;5;12m (https://github.com/dillonhuff/ahaHLS) - 2019, An open source high level synthesis (HLS) tool using LLVM[39m
[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;14m[1mcombinatorylogic/soc[0m[38;5;12m (https://github.com/combinatorylogic/soc) - 2019, An experimental System-on-Chip with a custom compiler toolchain.[39m
[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;14m[1mQuokka[0m[38;5;12m (https://github.com/EvgenyMuryshkin/QuokkaEvaluation) - C# to HL RTL translator[39m
[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;14m[1mVitis[0m[38;5;12m (https://github.com/Xilinx/HLS) - LLVM based, made by Xilinx. [39m[38;5;14m[1muser manual[0m[38;5;12m (https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_2/ug1399-vitis-hls.pdf)[39m
[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;14m[1mXLS[0m[38;5;12m (https://google.github.io/xls/) - 2020, HLS toolchain from Google[39m


[38;2;255;187;0m[4mOther HDL languages[0m

[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;14m[1mact[0m[38;5;12m (https://github.com/asyncvlsi/act) - asynchronous circuit/compiler tools[39m
[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;14m[1mautopiper[0m[38;5;12m (https://github.com/google/autopiper)[39m
[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;14m[1mSilice[0m[38;5;12m (https://github.com/sylefeb/Silice) - A language for hardcoding algorithms into FPGA hardware[39m
[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;14m[1mTL-Verilog[0m[38;5;12m (https://makerchip.com) - 2015+, Supports "timing-abstract" and "transaction-level design" methodologies; supported by proprietary and open-source tools[39m


[38;2;255;187;0m[4mHardware Intermediate Representations[0m

[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;14m[1mCIRCT[0m[38;5;12m (https://circt.llvm.org) - 2020+, LLVM / MLIR framework "Circuit IR Compilers and Tools"[39m
[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;14m[1mcoreir[0m[38;5;12m (https://github.com/rdaly525/coreir) - 2016-?, LLVM HW compiler## License[39m
[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;14m[1mlgraph[0m[38;5;12m (https://github.com/masc-ucsc/lgraph) - 2017-?, A Multi-Language Synthesis and Simulation IR for Hardware Design[39m
[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;14m[1mfirrtl[0m[38;5;12m (https://github.com/freechipsproject/firrtl) - 2016-?, Flexible Intermediate Representation for RTL[39m
[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;14m[1mLLHD[0m[38;5;12m (https://github.com/fabianschuiki/llhd) - Low Level Hardware Description — A foundation for building hardware design tools[39m
[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;14m[1mSpyDrNet[0m[38;5;12m (https://byuccl.github.io/spydrnet/) - 2019+, Framework for parsing and manipulating structural netlists in Python [39m
[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;14m[1mVLSIR[0m[38;5;12m (https://github.com/Vlsir/Vlsir) - IC Interchange Formats, defined in Google Protobuf SDL[39m

[38;2;255;187;0m[4mSynthesis tools[0m

[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;14m[1mvtr-verilog-to-routing[0m[38;5;12m (https://github.com/verilog-to-routing/vtr-verilog-to-routing)[39m
[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;14m[1myosys[0m[38;5;12m (https://github.com/YosysHQ/yosys) - RTL synthesis framework[39m


[38;2;255;187;0m[4mVisualization and Documentation generators[0m

[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;14m[1mbitfield[0m[38;5;12m (https://github.com/drom/bitfield) - Javascript bit field diagram renderer[39m
[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;14m[1md3-wave[0m[38;5;12m (https://github.com/Nic30/d3-wave) - Javascript wave graph visualizer for RTL simulations[39m
[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;14m[1md3-hwschematic[0m[38;5;12m (https://github.com/Nic30/d3-hwschematic) - Javascript hierarchical schematic visualizer for HDLs[39m
[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;14m[1mwavedrom[0m[38;5;12m (https://github.com/drom/wavedrom) - Javascript wave graph visualizer for documentations and sim.[39m
[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;14m[1mnetlistsvg[0m[38;5;12m (https://github.com/nturley/netlistsvg) - Javascript schematic visualizer[39m
[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;14m[1msphinx-hwt[0m[38;5;12m (https://github.com/Nic30/sphinx-hwt) - Plugin for sphinx documentation generator which adds schematic into html documentation.[39m
[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;14m[1mVisual Debug[0m[38;5;12m (https://redwoodeda.com/viz) - Custom simulation visualization framework, available within the [39m[38;5;14m[1mMakerchip.com[0m[38;5;12m (https://makerchip.com) IDE.[39m


[38;2;255;187;0m[4mHDL parsers[0m

[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;14m[1mhdlConvertor[0m[38;5;12m (https://github.com/Nic30/hdlConvertor) - Fast (System) Verilog/VHDL parser written as C++ extension for Python[39m
[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;14m[1mpyVHDLParser[0m[38;5;12m (https://github.com/Paebbels/pyVHDLParser) - VHDL parser written in Python[39m
[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;14m[1mrust_hdl[0m[38;5;12m (https://github.com/kraigher/rust_hdl) - VHDL parser and language server written in Rust[39m
[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;14m[1msv-parser[0m[38;5;12m (https://github.com/dalance/sv-parser) -  IEEE 1800-2017 System Verilog Parser written in Rust[39m
[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;14m[1mverible[0m[38;5;12m (https://chipsalliance.github.io/verible/) - Verible provides a SystemVerilog parser, style-linter, and formatter.[39m
[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;14m[1mslang[0m[38;5;12m (https://github.com/MikePopoloski/slang) - SystemVerilog compiler and language service.[39m
[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;14m[1mpyverilog[0m[38;5;12m (https://github.com/PyHDI/Pyverilog) - Python-based Hardware Design Processing Toolkit for Verilog HDL[39m
[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;14m[1mSurelog[0m[38;5;12m (https://github.com/chipsalliance/Surelog) - SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. [39m

[38;2;255;187;0m[4mOther Simulation tools[0m

[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;14m[1mmidas[0m[38;5;12m (https://github.com/ucb-bar/midas) - FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL[39m
[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;14m[1mcocotb[0m[38;5;12m (https://github.com/potentialventures/cocotb) - A coroutine based co-simulation library for writing VHDL and Verilog testbenches in Python[39m
[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;14m[1mosvvm[0m[38;5;12m (https://github.com/OSVVM/OsvvmLibraries) -  A VHDL verification framework, verification utility library, verification component library, and a simulator independent scripting flow[39m
[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;14m[1muvvm[0m[38;5;12m (https://github.com/OSVVM/OsvvmLibraries) - A free and Open Source Methodology and Library for VHDL verification of FPGA and ASIC.[39m

[38;2;255;187;0m[4mOther Design Automation tools[0m

[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;14m[1mpeakrdl[0m[38;5;12m (https://github.com/SystemRDL/PeakRDL) - CSR toolchain to generate RTL, UVM RAL models, docment(html and markdown), IPXACT, c header from SystemRDL or IPXACT.[39m
[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;14m[1mRgGen[0m[38;5;12m (https://github.com/rggen/rggen) - Code generator tool to generate RTL, UVM RAL models and Wiki documents from CSR specifications[39m
[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;14m[1msv-tests[0m[38;5;12m (https://symbiflow.github.io/sv-tests) - Test suite designed to check compliance with the SystemVerilog standard[39m
[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;14m[1mtbengy[0m[38;5;12m (https://github.com/prasadp4009/tbengy) - Code generator tool to generate SV/UVM RTL and Testbech as well scripts with support for bitstream generation for Digilent FPGAs[39m
[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;14m[1mHDLGen[0m[38;5;12m (https://github.com/WilsonChen003/HDLGen) - Tool for processing of embedded Perl or Python scripts in Verilog source code.[39m
[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;14m[1mfusesoc[0m[38;5;12m (https://github.com/olofk/fusesoc) -  Package manager and a set of build tools for HDL.[39m
[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;14m[1mbender[0m[38;5;12m (https://github.com/pulp-platform/bender) -  Dependency management tool for hardware design projects.[39m
[48;5;12m[38;5;11m⟡[49m[39m[38;5;12m [39m[38;5;14m[1mhbs[0m[38;5;12m (https://github.com/m-kru/hbs) - A lean dependency management and build system for hardware description projects.[39m

[38;2;255;187;0m[4mLicense[0m

[38;5;14m[1m![0m[38;5;12mCC0[39m[38;5;14m[1m (http://mirrors.creativecommons.org/presskit/buttons/88x31/svg/cc-zero.svg)[0m[38;5;12m (https://creativecommons.org/publicdomain/zero/1.0/)[39m

[38;5;12mTo the extent possible under law, [39m[38;5;14m[1mAliaksei Chapyzhenka[0m[38;5;12m (http://drom.io) has waived all copyright and related or neighboring rights to this work.[39m
